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MM74C905 12-Bit Successive Approximation Register
October 1987 Revised January 1999
MM74C905 12-Bit Successive Approximation Register
General Description
The MM74C905 CMOS 12-bit successive approximation register contains all the digit control and storage necessary for successive approximation analog-to-digital conversion. Because of the unique capability of CMOS to switch to each supply rail without any offset voltage, it can also be used in digital systems as the control and storage element in repetitive routines.
Features
s Wide supply voltage range: s Guaranteed noise margin: s High noise immunity: 3.0V to 15V 1.0V 0.45 VCC (typ) Fan out of 2 driving 74L
s Low power TTL compatibility:
s Provision for register extension or truncation s Operates in START/STOP or continuous conversion mode s Drive ladder switches directly. For 10 bits or less with 50k/100k R/2R ladder network
Ordering Code:
Order Number MM74C905N Package Number N24A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600" Wide
Connection Diagram
Pin Assignments for DIP
(c) 1999 Fairchild Semiconductor Corporation
DS005910.prf
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MM74C905
Truth Table
Time tn 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X
H = HIGH Level L = LOW Level X = Don't Care NC = No Change
Inputs S L H H H H H H H H H H H H H X X E L L L L L L L L L L L L L L L H D0 X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X Q11 X L D11 D11 D11 D11 D11 D11 D11 D11 D11 D11 D11 D11 D11 H Q10 X H L D10 D10 D10 D10 D10 D10 D10 D10 D10 D10 D10 D10 NC Q9 X H H L D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 NC Q8 X H H H L D8 D8 D8 D8 D8 D8 D8 D8 D8 D8 NC Q7 X H H H H L D7 D7 D7 D7 D7 D7 D7 D7 D7 NC
Outputs Q6 X H H H H H L D6 D6 D6 D6 D6 D6 D6 D6 NC Q5 X H H H H H H L D5 D5 D5 D5 D5 D5 D5 NC Q4 X H H H H H H H L D4 D4 D4 D4 D4 D4 NC Q3 X H H H H H H H H L D3 D3 D3 D3 D3 NC Q2 X H H H H H H H H H L D2 D2 D2 D2 NC Q1 X H H H H H H H H H H L D1 D1 D1 NC Q0 X H H H H H H H H H H H L D0 D0 NC CC X H H H H H H H H H H H H L L NC
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MM74C905
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin Operating Temperature Range (TA) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range 700 mW 500 mW 3.0V to 15V -0.3V to VCC+0.3V -40C to +85C -65C to +150C
Absolute Maximum VCC Lead Temperature (TL) (Soldering, 10 seconds)
16V 260C
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) ISOURCE ISOURCE ISINK ISINK Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Logical "1" Input Current Logical "0" Input Current Supply Current Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) RSOURCE RSINK Q11-Q0 Outputs Q11-Q0 Outputs VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V, IO = -10 A VCC = 10V, IO = -10 A VCC = 5.0V, IO = 10 A VCC = 10V, IO = 10 A VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V VCC = 4.75V VCC = 4.75V VCC = 4.75V, IO = -360 A VCC = 4.75V, IO = 360 A VCC = 5.0V, VOUT = 0V TA = 25C VCC = 10V, VOUT = 0V TA = 25C VCC = 5.0V, VOUT = VCC TA = 25C VCC = 10V, VOUT = VCC TA = 25C VCC = 10V 5% VOUT = VCC - 0.3V TA = 25C VCC = 10V 5% VOUT = 0.3V TA = 25C 80 230 150 350 8.0 16 mA 1.75 3.6 mA -8.0 -15 mA -1.75 -3.3 2.4 0.4 VCC - 1.5 0.8 -1.0 0.005 -0.005 0.05 300 4.5 9.0 0.5 1.0 1.0 3.5 8.0 1.5 2.0 V V V V V V V V A A A V V V V mA Parameter Conditions Min Typ Max Units
CMOS/LPTTL INTERFACE
OUTPUT DRIVE (See Family Characteristics Data Sheet)
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MM74C905
AC Electrical Characteristics
TA = 25C, CL = 50 pF, unless otherwise specified Symbol tpd Parameter Propagation Delay Time from Clock Input to Outputs (Q0-Q11) (tpd(Q) ) tpd tpd Propagation Delay Time from Clock Input to D0 (tpd(D0)) Propagation Delay Time from Register Enable (E) to Output (Q11) (tpd(E)) tpd tS tS tW tr, tf fMAX CCK CIN CPD Propagation Delay Time from Clock to CC (tpd(CC)) Data Input Set-Up Time Start Input Set-Up Time Minimum Clock Pulse Width Maximum Clock Rise and Fall Time Maximum Clock Frequency Clock Input Capacitance Input Capacitance Power Dissipation Capacitance
(Note 2)
Conditions Min Typ 200 80 180 70 190 75 190 75 80 30 80 30 250 100 125 50 15 5.0 2.0 5.0 4.0 10 10 5 100 Max 350 150 325 125 350 150 350 0.50 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s MHz MHz pF pF pF
VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V Clock Input (Note 3) Any other Input (Note 3) (Note 4)
Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics Application Note-- AN-90.
Typical Performance Characteristics
RSINK vs Temperature RSOURCE vs Temperature
*These points are guaranteed by automatic testing.
*These points are guaranteed by automatic testing.
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MM74C905
Timing Diagram
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MM74C905
Switching Time Waveforms
USER NOTES FOR A/D CONVERSION The register can be used with either current switches that require a low voltage level to turn the switch ON or current switches that require a high voltage level to turn the switch ON. If current switches are used which turn ON with a low logic level, the resulting digit output from the register is active low. That is, a logic "1" is represented as a low voltage level. If current switches are used which turn ON with a high logic level, the resulting digit output is active high. A logic "1" is represented as a high voltage level. For a maximum error of 1/2 LSB, the comparator must be biased. If current switches that require a high voltage level to turn ON are used, the comparator should be biased +1/2 LSB and if the current switches require a low logic level to turn ON, then the comparator must be biased -1/2 LSB. The register can be used to perform 2's complement conversion by offsetting the comparator one half full range +1/2
LSB and using the complement of the MSB Q11 as the sign bit. If the register is truncated and operated in the continuous conversion mode, a lock-up condition may occur on powerON. This situation can be overcome by making the START input the "OR" function of CC and the appropriate register output. The register, by suitable selection of register ladder network, can be used to perform either binary or BCD conversion. The register outputs can drive the 10 bits or less with 50k/ 100k R/2R ladder network directly for VCC = 10V or higher. In order to drive the 12-bit 50k/100k ladder network and have the 1/2 LSB resolution, the MM74C902 or MM74C904 is used as buffers, three buffers for MSB (Q11), two buffers for Q10, and one buffer for Q9.
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MM74C905
Typical Applications
12-Bit Successive Approximation A-to-D Converter, Operating in Continuous 8-Bit Truncated Mode
12-Bit Successive Approximation A-to-D Converter, Operating in Continuous Mode, Drives the 50k/100k Ladder Network Directly
Definition of Terms
CP: Register clock input. CC: Conversion complete--this output remains at VOUT(1) during a conversion and goes to VOUT(0) when conversion is complete. D: Serial data input--connected to comparator output in Ato-D applications. E: Register enable --this input is used to expand the length of the register. When E is at VIN(1) Q11 is forced to VOUT(1) and inhibits conversion. When not used for expansion E must be connected to VIN(0) (GND). Q11: True register MSB output. Q11: Complement of register MSB output. Qi (i = 0 to 11): Register outputs. S: Start input--holding start input at VIN(0) for at least one clock period will initiate a conversion by setting MSB (Q11) at VOUT(0) and all other output (Q10-Q0) at VOUT(1). If setup time requirements are met, a conversion may be initiated by holding start input at VIN(0) for less than one clock period. DO: Serial data output--D input delayed by one clock period.
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MM74C905 12-Bit Successive Approximation Register
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600" Wide Package Number N24A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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